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ALU (Aritmetic Logic Unit) Tasarımı Şematik ve Verilog

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  • Bu doküman başlangıç seviyesinde bir ALU nun tüm gereksinimlerini kapsamaktadır.Kodların hepsini ISE Xilinx de derledim ve Spartan 3 FPGA kartına gömdüm.Hiç bir sorunla karşılaşmadım. Bu dökümanda ben şematik şekilde de konuyu anlatıyorum. Eğer isterseniz siteye üye olduktan sonra bana pm atabilirsiniz (siteye üye olmadan pm atılmıyor). Her türlü sorunuzu yanıtlamaya çalışırım. Ve isterseniz programın derlenmiş halini de verebilirim test kodlarıyla birlikte. Alu zero, overflow, less i içermektedir.



    Bu resim 5 fonksiyonlu 32 bit bir ALU yu ve en değerlilikli biti göstermektedir.



    Bu resim 5 fonksiyonlu ve zero çıkışlı 32 bit ALUyu göstermektedir.



    Bu resim 6 fonksiyonlu less ve zerolu 32 bir ALU yu göstermektedir.

    Verilog kodu:::

    Carry look ahead:

    module carrybit(

    input [30:0] ag,

    input [30:0] bg,

    input ai,

    input bi,

    input c0,

    output [31:1] c

    );

    wire [30:0] a,b,g,p;

    assign a=(ai)?~ag:ag;

    assign b=(bi)?~bg:bg;

    assign g[30:0]=a[30:0] & b[30:0];

    assign p[30:0]=a[30:0] ^ b[30:0];

    assign c[1]=g[0] | (p[0] & c0);

    assign c[2]=g[1] | (p[1] & (g[0] | (p[0] & c0)));

    assign c[3]=g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))));

    assign c[4]=g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))));

    assign c[5]=g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))));

    assign c[6]=g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))));

    assign c[7]=g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))));

    assign c[8]=g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))));

    assign c[9]=g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))));

    assign c[10]=g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))));

    assign c[11]=g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))));

    assign c[12]=g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))));

    assign c[13]=g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))));

    assign c[14]=g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))));

    assign c[15]=g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))));

    assign c[16]=g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))));

    assign c[17]=g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))));

    assign c[18]=g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))));

    assign c[19]=g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))));

    assign c[20]=g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))));

    assign c[21]=g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))));

    assign c[22]=g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))));

    assign c[23]=g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))));

    assign c[24]=g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))));

    assign c[25]=g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))))));

    assign c[26]=g[25] | (p[25] & (g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))))))));

    assign c[27]=g[26] | (p[26] & (g[25] | (p[25] & (g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))))))))));

    assign c[28]=g[27] | (p[27] & (g[27] | (p[27] & (g[26] | (p[26] & (g[25] | (p[25] & (g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))))))))))))));

    assign c[29]=g[28] | (p[28] & (g[27] | (p[27] & (g[27] | (p[27] & (g[26] | (p[26] & (g[25] | (p[25] & (g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))))))))))))))));

    assign c[30]=g[29] | (p[29] & (g[28] | (p[28] & (g[27] | (p[27] & (g[27] | (p[27] & (g[26] | (p[26] & (g[25] | (p[25] & (g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));

    assign c[31]=g[30] | (p[30] & (g[29] | (p[29] & g[28] | (p[28] & (g[27] | (p[27] & (g[27] | (p[27] & (g[26] | (p[26] & (g[25] | (p[25] & (g[24] | (p[24] & (g[23] | (p[23] & (g[22] | (p[22] & (g[21] | (p[21] & (g[20] | (p[20] & (g[19] | (p[19] & (g[18] | (p[18] & (g[17] | (p[17] & (g[16] | (p[16] & (g[15] | (p[15] & (g[14] | (p[14] & (g[13] | (p[13] & (g[12] | (p[12] & (g[11] | (p[11] & (g[10] | (p[10] & (g[9] | (p[9] & (g[8] | (p[8] & (g[7] | (p[7] & (g[6] | (p[6] & (g[5] | (p[5] & (g[4] | (p[4] & (g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));

    endmodule

    Multiplexer:

    module mux4×1(

    input a,

    input b,

    input c,

    input d,

    input s1,

    input s0,

    output y

    );

    wire s1d,s0d,ak,bk,ck,dk;

    not (s1d,s1);

    not (s0d,s0);

    and (ak,s1d,s0d,a);

    and (bk,s1d,s0,b);

    and (ck,s1,s0d,c);

    and (dk,s1,s0,d);

    or (y,ak,bk,ck,dk);

    endmodule

    ALU1 bit:

    module Alu(

    input a,

    input b,

    input c,

    input less,

    input [3:0] operant,

    output result

    );

    wire ak,bk,xab,ve,veya,toplam;

    xor(ak,a,operant[3]);

    xor(bk,b,operant[2]);

    and(ve,ak,bk);

    or(veya,ak,bk);

    xor (xab,ak,bk);

    xor (toplam,xab,c);

    mux4×1 m(ve,veya,toplam,less,operant[1],operant[0],result);

    endmodule

    ALU significant bit:

    module Alulast(

    input a,

    input b,

    input c,

    input less,

    input [3:0] operant,

    output sonuc,

    output toplam,

    output overflow

    );

    wire ak,bk,xab,ve,veya;

    xor(ak,a,operant[3]);

    xor(bk,b,operant[2]);

    and(ve,ak,bk);

    or(veya,ak,bk);

    xor(xab,ak,bk);

    xor(toplam,xab,c);

    everflow t(a,b,toplam,overflow);

    mux4×1 m(ve,veya,toplam,less,operant[1],operant[0],sonuc);

    endmodule

    ALU 32 bit

    module Alu32(

    input [31:0] a,

    input [31:0] b,

    input [3:0] operant,

    output [31:0] s,

    output zero

    );

    wire[31:1]c;

    wire tplm,overflow;

    carrybit e(a[30:0],b[30:0],operant[3],operant[2],operant[2],c);

    Alu a00(a[0],b[0],operant[2],tplm,operant,s[0]),

    a01(a[1],b[1],c[1],1′b0,operant,s[1]),

    a02(a[2],b[2],c[2],1′b0,operant,s[2]),

    a03(a[3],b[3],c[3],1′b0,operant,s[3]),

    a04(a[4],b[4],c[4],1′b0,operant,s[4]),

    a05(a[5],b[5],c[5],1′b0,operant,s[5]),

    a06(a[6],b[6],c[6],1′b0,operant,s[6]),

    a07(a[7],b[7],c[7],1′b0,operant,s[7]),

    a08(a[8],b[8],c[8],1′b0,operant,s[8]),

    a09(a[9],b[9],c[9],1′b0,operant,s[9]),

    a10(a[10],b[10],c[10],1′b0,operant,s[10]),

    a11(a[11],b[11],c[11],1′b0,operant,s[11]),

    a12(a[12],b[12],c[12],1′b0,operant,s[12]),

    a13(a[13],b[13],c[13],1′b0,operant,s[13]),

    a14(a[14],b[14],c[14],1′b0,operant,s[14]),

    a15(a[15],b[15],c[15],1′b0,operant,s[15]),

    a16(a[16],b[16],c[16],1′b0,operant,s[16]),

    a17(a[17],b[17],c[17],1′b0,operant,s[17]),

    a18(a[18],b[18],c[18],1′b0,operant,s[18]),

    a19(a[19],b[19],c[19],1′b0,operant,s[19]),

    a20(a[20],b[10],c[20],1′b0,operant,s[20]),

    a21(a[21],b[21],c[21],1′b0,operant,s[21]),

    a22(a[22],b[22],c[22],1′b0,operant,s[22]),

    a23(a[23],b[23],c[23],1′b0,operant,s[23]),

    a24(a[24],b[24],c[24],1′b0,operant,s[24]),

    a25(a[25],b[25],c[25],1′b0,operant,s[25]),

    a26(a[26],b[26],c[26],1′b0,operant,s[26]),

    a27(a[27],b[27],c[27],1′b0,operant,s[27]),

    a28(a[28],b[28],c[28],1′b0,operant,s[28]),

    a29(a[29],b[29],c[29],1′b0,operant,s[29]),

    a30(a[30],b[30],c[30],1′b0,operant,s[30]);

    Alulast a31(a[31],b[31],c[31],1′b0,operant,s[31],tplm,overflow);

    assign zero=~(|s[31:0]);

    endmodule

    kusura bakmayın resimler çıkmıyor.sitesinden bakın isterseniz.

    alıntı:http://tobedifferent.net/electronic/alu-aritmetic-logic-unit-tasarimi-sematik-ve-verilog/



    < Bu mesaj bu kişi tarafından değiştirildi ymury -- 23 Nisan 2010; 1:18:43 >



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  • Kardeşim,bu ALU tasarımındaki resimleri görüntüleyemiyorumda,bana bi yardımın dokunur mu ?Birde programın derlenmiş halini yollayabilirsen sevinirim.Şimdiden teşekkürler...
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